Xilinx ISE Schematic Capture

The Xilinx ISE tools allow you to use schematics, hardware description languages (HDLs), and specially designed modules in a number of ways.  This tutorial discusses hierarchical schematic designs.  In this tutorial you will enter the schematic of a full adder and perform a functional simulation.  We use the full adder to make a macro symbol, and use it to construct a four bit ripple carry adder. Some readers will rightly object to the example in that it fails to make use of hardware features available in modern FPGAs.  The point however, is to get you started on an adventure, using the tools.  The first step of a long journey need not be high-tech. 

If you are working in the United Techology Building or Dana Building, ask for a folder on the ECE department server.  The COE File Server is available to students enrolled in College of Engineering courses.

Before starting the Xilinx ISE tools for the first time, manually set aside a directory for your projects.  If you are working at home, you will probably pick the C: drive.  Double click the My Computer icon and then double click to open the drive you want. With the mouse select:

File => New => Folder

Starting ISE

In this tutorial the new folder is named ISE.  To start Xilinx WebPACK ISE, either double click on the window icon matching that shown below, or make the following selection:

Start => All Programs => Xilinx WebPACK => WebPACK Project Manager

WebPACK Project Navigator icon

Once the project navigator window is open, make a new project.  Use the mouse to select:

File => New Project
In the new project window, enter data so the fields look like the following, then click OK.  If you are on campus and have the ECE department file server mapped as disk F: then make the necessary substitution. 


New Project window

Entering the Schematic

Next, make a new schematic.  In the project navigator window, use the mouse to select:

Project => New Source

In the new source window, enter data so the fields look like the following, then click Next.  Next click Finish to produce the new schematic and open the schematic editor ECS. 


New Source window

Before we caught up in details, the following is the full-adder circuit that you will be entering:


Full adder schematic

The Xilinx ECS schematic capture tool opens and a new entry named fadd appears in the sources pane, in the upper left part of the project navigator window.  The next step is to insert components into the schematic and then use wires to interconnect the components. 

In the categories pane to the right side of the ECS window, use the mouse to select the entry logic


Component categories

Next, in the symbol window, use the mouse to select the two input XOR gate named xor2.


Component symbols

The schematic editor is said to have mode, the selection you just made changes to the place components mode.  In this mode, the mouse arrow is replaced with cross-hairs and has a component attached.  To exit this mode, either press the escape key or click the pointer icon.


Pointer icon

To place a component in the schematic, select a component from the component symbols list as described above.  Next, move the mouse pointer to the schematic, click left, and move the mouse to reveal the placed component.  Place two xor2 components, and below them three and2 components.  Finally, slightly to the lower right place an or3 component. 

In normal mode ( press the escape key to exit component mode ), components in the schematic are easily moved about.  Point and left click to select a component.  Once selected, point at the component, press and hold the left mouse button, and then drag the mouse to a new location.  Multiple components can be selected and moved in this way.  If you press the shift key and select another component, the previous component remains selected.  If you point the mouse away from any components, press and hold the left mouse button, and drag the mouse, a selection box appears.  In releasing the left mouse button, all components in the selection box are selected.

To zoom in on a selected part of a schematic, either press F9 or select the following:

View => Zoom => To Box
Place the mouse cross-hairs just above and to the left of the components you placed.  Press and hold the left mouse button and drag the mouse so a box appears around the components, and then release the left mouse button. In zoom mode, the mouse arrow is replaced with cross-hairs.  To exit this mode, either press the escape key or click the pointer icon.

Newly placed components

Notice how the pull-down menu lists the corresponding function key for each zoom function.  To return to the full schematic view, either press F6 or select:

View => Zoom => Full View

The next step is adding wires, and then adding I/O markers.  To wire one device terminal to another first change to the wire mode.  This can be done several ways.


Add Wire Icon

Once in the wire mode, the icon changes to cross-hairs.  Move the cross-hairs to the upper left XOR gate output pin till tiny red boxes appear, and left click the mouse.  Move the cross-hairs to the upper input gate of the right XOR gate.  Left click the mouse so a wire is placed. 


First wire placed

Add additional wires so the circuit looks like the figure below.  To place a bend in a wire, left click.  To move a wire, first press the escape key to change to the normal mode.  Next point and left click to select a wire and then use the mouse to drag the wire.

Add additional wires so the circuit looks similar to the following.  To attach a wire to another to form a connection point, point at the wire and left click. 

A dangling wire has a connection one end only.  There are two methods to place a dangling wire.  Start by changing to the wire mode.

Add dangling wires so the circuit looks like the following:

Next, add I/O markers.  To switch to the I/O marker mode do one of the following:


I/O Marker Icon

The cursor changes to cross-hairs with an attached marker icon.  Set the input direction radio buttons to input

Point the cross-hairs at the upper left dangling wire end and left click to place an I/O marker.  In a similar fashion, attach two more input I/O markers.


Press the escape key to return to normal mode.  Double-click the upper I/O marker to open the Object Properties window.  In the name field change the entry to Xin

In similar fashion, change the names of the middle and lower I/O markers to Yin and Cin, respectively.

Switch to the I/O marker mode and set the direction radio button to output.  Attach an I/O marker to each of the remaining two dangling wires.  Assign the name Sum to the upper output I/O marker and Cout to the lower output I/O marker. 

Add a Title Block

To add a title block to the schematic, select the General category and pick the tblock component.  Place the title block near the lower right corner of the schematic.  Zoom in to get a better view of the title block.  Use one of the following methods to change to the Add Text mode.


Add Text Icon

Enter your name in the Attribute Name field


Attribute Name Field

Move the cursor to the comments field in the title block and left click.  Similarly, enter the title and the current date.  The title block will look similar to the following:


Example Title Block

The schematic is now completed.  Below the ECS title bar, click

File => Save

Functional Simulation

We will perform a functional simulation next.  ISE allows simulation to be performed using either a hand-coded test bench or one generated by the Xilinx HDL Bencher tool.  The HDL Bencher tool provides a simple graphical means to describe stimulus and the expected response.  In the Project Navigator window, select the following:

Project => New Source

In the New dialog box, highlight the Test Bench Waveform entry, enter fadd_tb into the File Name field, verify that the Add to Project box is checked, and then click Next.  The Select dialog box used to choose the top-most design module, the entry fadd should already be highlighted.  Click the Next button.

This next dialog box summarizes all data entered thus far and gives you a last chance to back-up to make changes.  Click Finish to start the HDL Bencher tool.  In the Initialize Timing dialog box, verify that the button indicating a combinatorial design is checked, along with the values listed.  Click OK.

With this timing the basic unit of simulated time will be 100ns.  In this example you will manually set the input values for each time interval.  To set the input to 001b at time 100ns, point to the center of the time interval and left click.


Setting input bit high

Continue, setting the values in the following intervals to 010b, 011b, 100b, 101b, 110b, and 111b, respectively.  In the HDL Bencher window, use the mouse to select:

File => Save
Next, clock the Bencher window
File => Exit

In the upper left pane of the Project Navigator window, click left to highlight the file fadd_tb.tbw.  In the Processes pane, to the left of the Project Navigator window, right-click on Generate Expected Results and in the pop-up window select Run.  If you cannot see the entry, left click the + icon to left of the toolbox icon for ModelSim Simulator.  In a few moments the simulator writes the simulated results and re-opens the HDL Bencher program to display the results.  Be sure to examine the results.


Simulation Results

Take a moment to closely examine the first few time intervals.  Given the inputs, the results appear a few moments later.  To see more of the simulation, the Waveform Viewer may be resized and the time scale an be zoomed in or out. 


Zoom in and out buttons

Create a New Symbol

In the ECS window select the following:
Tools => Create Symbol
Examine the entries in the Create Symbol window then click OK. 

The new window that appears gives you an opportunity to make changes to the new symbol.  No changes are needed here, so close the symbol file.

File => Close

A Four-Bit Adder

In the Project Navigator window open a new schematic and name it fourbit.  In the Categories pane click to select <c:/ise/adder> and in the Symbols pane select fadd.  Move the cross-hairs and place four instances of the full-adder.  Insert wires to connect each Cout pin to its next Cin pin.  From the General category insert a ground symbol and wire it to the lower Cin pin. 

A bus is made, first by placing a wire in the schematic and then naming the wire as a bus.  Look at the figure below to see how to place the wire.  To end the wire, left click to place a bend, then press the escape key.  Next, attach the I/O marker, and press the escape to return to normal mode.  Double click the I/O marker and in the pop-up window change the name field entry to Xval(3:0)


Naming an I/O block for a bus


A first bus

Attach four bus tap icons to the bus wire

and add a wire from each to the full-adder Xin pins.

Each of these new wires must next be named.  Double click the upper bus-tap wire and change the name field to Xval(3).  Then click OK.

In similar fashion, name the remaining bus-tap wires, in successive downward fashion as the following, respectively.

To check the schematic, select the following:
Tools => Check Schematic
If an error is reported, click the report entry so a yellow report marker appears in the schematic.  A correct schematic will not have any errors reported.  In the same fashion as above, add another bus with an input I/O block named Yval(3:0).  In successive fashion from top to bottom, name the bus-tap wires:

Add a bus with an output I/O block named Sum(3:0).  Likewise, in successive fashion from top to bottom, name the bus-tap wires:

Attach a wire to the upper right carry-out pin and an output I/O block pin.  Name the I/O block pin Cout.

To finish the schematic, add a title block and insert your name and title 'fourbit'.  Add a test-bench waveform file named 'fourbit_tb'.  The following are sample simulation results.  To display results in Hexadecimal, click the corresponding button.


Copyright Notice

This tutorial page is written for computer engineering students at the University of Hartford.  Copyright is reserved by the author, but copies of this document may be made for educational use as-is, provided that this statement remains attached.  The original version of this tutorial was written in great haste.  Later versions result from periodic improvement.  Constructive criticism is welcome and may be credited. 

Original Author: Jonathan Hill (jmhill@hartford.edu)
Original Copyright Date: Thu Jan 23 01:00:15 EST 2003
Last Modified By: Jonathan Hill (jmhill@hartford.edu)
Last Modified Date: Fri Feb 7 14:53:51 EST 2003