The delay for a single gate is easily understood. There is a manufacturer defined threshold voltage Vt. Propagation delay for a single gate is the time from when the input crosses Vt to when the output crosses Vt. In the following figure, a rectangular input pulse IN is applied to a number of gates. The signal X1 is high and X2 is low. By convention, the naming of the propagation delay metrics is named relative to the gate output.
Propagation delay for a simple gate may be characterized with two or three values. The minimum delay is generally not specified for non-performance logic families such as TTL.
The following are the typical and maximum delay values for the 74LS00 NAND gate. Other TTL delay values can be found in the data sheets for the corresponding TTL family.
Typical | Maximum | ||
t_{pLH} | 9ns | 15ns | |
t_{pHL} | 10ns | 15ns |
We next generalize the idea of propagation delay for more complicated circuits.
Reconsider the gates above, the delay path in the AND gate and the NAND gate is active only when X1 is high. The delay path in the OR and NOR gate is active only when X2 is low. To see why this is so, examine the corresponding truth table. With input A low the AND and NAND outputs are unchanging. Conversely, with A high the OR and NOR outputs are unchanging.
A | B | A and B | A nand B | A or B | A nor B | ||||
0 | 0 | 0 | 1 | 0 | 1 | ||||
0 | 1 | 0 | 1 | 1 | 0 | ||||
1 | 0 | 0 | 1 | 1 | 0 | ||||
1 | 1 | 1 | 0 | 1 | 0 |
Consider the next, more interesting circuit in Figure 1. We pick B to be the input and Z is the output. For the delay path illustrated to propagate a signal through the AND gate, A must be high. To propagate through the NAND gate, Y must be high, hence either C or D must be high. One set of inputs is illustrated.
A timing diagram is used to illustrate timing along the delay path. Figure 3 is the corresponding timing diagram. The notation "nom (max)" as in "10(15)" means that the nominal or typical delay is 10ns and the maximum delay is less than 15ns. The propagation delay threshold is selected so the sum of the propagation delays for each gate is approximately equal to the delay along the delay path.
In some circumstances we may need to minimize the propagation delay along a specific path. In such cases a timing diagram is very helpful. In other cases, the idea of settle time is more important. The following multiplexer circuit should make the point. Given that the inputs X and Y are both high, regardless of the select value S, the output F should be high.
In examining the timing diagram, we discover that there are two active delay paths. Each delay path produces one change in the output, causing the dynamic behavior to be more interesting. The dashed lines help to make the causality relationships between inputs and outputs more obvious. Such spurious output is called a glitch.
For a circuit with more than one delay path or having multiple inputs changing simultaneously, it will take time for the output to come to rest, producing the final correct output. We call this the settle time. In Figure 5 the settle time is typically 31ns but the maximum delay is less than 52ns.
We can use the idea of settle time to characterize the delay of an entire circuit For a logic circuit with no internal feedback, given a change to any input or combination of inputs, the worst case settle time is the longest propagation delay for all delay paths through the circuit. One problem with using timing diagrams to estimate settle time is the effort involved. For a quick estimate of the settle time we can resort to the sum of worst case delays (SWC) analysis.
To perform a simplified worst case analysis of the settle time of a combinational logic circuit with no internal feedback, we estimate the worst case delays by taking the sum of the worst case (SWC) delays of components, independent of the signal transition, low to high or high to low. Consider the following half-adder circuit.
As shown in Figure 6, the first step in performing an SWC analysis is writing next to each gate its worst case propagation delay. Identify delay paths from each input to each output. There are two paths from A to S, two paths from B to S, but only one path from A to C and one path from B to C.
Figure 7a: Paths from A to S,C |
Figure 7b: Paths from B to S,C |
Next, identify the longest path from each input to each output. If all the gates have approximately the same worst case delay, pick the path with the most number of gates. Otherwise, add up the delays for each path and pick the path with the largest sum.
Summarize the delays in a table. To read Table 1, go to the row corresponding to a given input, then go across the row to find the SWC delay for the path to the desired output.
S | C | |
A | 42ns | 30ns |
B | 42ns | 30ns |
Examine the summary table to find the largest entry. The largest entry is referred to as the worst case SWC delay. We will use the worst case SWC delay as an estimate of the settle time. In the half-adder example the worst case SWC delay is 42ns.
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Author: Jonathan Hill jmhill at hartford dot edu