New project name
For detail on installing the software and using the software on campus, please refer to Part 0 of this tutorial. Before starting the Xilinx ISE tools for the first time, manually set aside a directory for your projects. Click the start icon and open the "My Computer" icon or windows navigator. If you are working at home, double click to open the C: drive. If you are working in lab, either double click the Z: drive for the CETA file server, or other drive letter if you are using a FLASH memory device. In the new window, right-click and select:
New => Folderand assign a name such as 'IseWork'.
To start ISE/Webpack, on the desktop click left to select the following:
Start => Programs => Xilinx ISE => Project NavigatorIf a 'Tip of the Day' window pops up, click 'OK' to close it. In the Xilinx - ISE project navigator window, click left to make a new project:
File => New Project...The first pop-up window will look like the following. Click 'Next'.
The next pop-up window involves selecting a part and several other options. Click 'Next'.
The next window provides an opportunity to make new files, for now just click 'Next'. The next window provides an opportunity to add files to the new project, for now click 'Next'. The general flow with Xilinx tools is that a series of input windows is followed by a summary window, that provides a last chance to check your input. Check the values then click, 'Finish'.
Next, make a new schematic. In the project navigator window, use the mouse to select:
Project => New Source...In the pop-up window, click the 'Schematic' icon and enter 'fadd' in the filename field. Make sure the 'Add to project' item is checked, then click 'Next' and then 'Finish'. After a few moments a new schatic window will appear and then may be covered by the project status window. Click to minimize the project status window, then adjust the size of the schematic editor window.
Before we caught up in details, the following is the full-adder circuit that you will be entering:
With the AND2 gate selected, when you move the mouse to point in the schematic editor, an instance of a two input AND gate appears. Click left to place the AND gate into your schematic, and then click to insert two more AND gates. Continue, inserting an OR3 gate and two XOR2 gates, so the schematic looks similar to the following:
To get a better view of the components, you can zoom in or out the view. The zoom-to-box choice has you use the mouse to draw a box to define the level of zoom. The zoom-to-full-view zooms out to display the entire schematic. The zoom-to-seleted zooms to display the selected component.s
View => Zoom => In View => Zoom => Out View => Zoom => To Box View => Zoom => To Full View View => Zoom => To Selected
The next step is adding wires, and then adding I/O markers. To wire one device terminal to another first change to the wire mode. This can be done several ways:
Once in the wire mode, the icon changes to cross-hairs. Move the cross-hairs to the upper left XOR gate output pin till tiny boxes appear, and left click the mouse. Move the cross-hairs to the upper input gate of the right XOR gate. Left click the mouse so a wire is placed.
Add additional wires so the circuit looks like the figure below. To place a bend in a wire, left click. To move a wire, first press the escape key to change to the normal mode. Next point and left click to select a wire and then use the mouse to drag the wire. To attach a wire to another to form a connection point, point at the wire and left click.
A dangling wire has a connection one end only. There are two methods to place a dangling wire. Start by changing to the wire mode, using a technique described above.
Add dangling wires so the circuit looks like the following:
Next, add I/O markers. To switch to the I/O marker mode do one of the following:
I/O Marker Icon
Add => I/O Marker
The cursor changes to cross-hairs with an attached marker icon. In the process pance, click the I/O marker direction radio buttons to Add an input marker. Point the cross-hairs at the upper left dangling wire end and left click to place an I/O marker. In a similar fashion, attach markers to other two dangling wires to the left.
Double click the upper left marker and in the pop-up window enter the name 'cin' into the Net Atribute Name field and then click 'OK'. Likewise, assign the names 'ain' and 'bin' to the middle and lower marker.
Enter marker mode again, this time in the process pane, click to select 'Add an output marker'. Attach markers to the dangling wires to the right, and this time assign the names 'cout' and 'sum' to upper right and lower right dangling wires, respectively.
To add a title block to the schematic, click the 'Add Icon' button to enter the corresponding mode, select the General category, and pick the title component. Place the title block near the lower right corner of the schematic. Zoom in to get a better view of the title block. Next, double click the title block icon and in the pop-up window, enter the following into each field, then click 'OK'.
You will notice that the upper left pane has a choice as to what to consider the files for. The choice 'Synthesis/Implementation' should be displayed. When a file name in the upper left pane is selected, it becomes highlighed. The use choice and type of file selected determines what choices you have in the lower left Processes pane. In the upper left pane, click left to highlight and select the name fadd.vhd.
In the lower left pane, right click on the keyword Synthesize. In the pop-up window select the entry Run to run the synthesis tool. The synthesis tool verifies the syntax of the VHDL code and generates an intermediate form that we use to perform simulation. The intermediate form is used later to implement the design.
A yellow question mark indicates an uncertain result and a red 'X' mark indicates an error. Suppose an error occurred. In the lower window, use the slider to review the synthesis output. In the case of a syntax error, double left click the corresponding link to cause the text editor to display an arrow near the error. The error might be on previous line, so look carefully.&nbp; After correcting and saving the design file, try synthesis again. A green check symbol indicates success.
The synthesis tool also produces a useful report file. To the left of the Synthesize keyword, click the '+' box to expand the list. Double click on View Synthesis Report.
In addition to summarizing errors and warnings, the report contains a summary of information used and produced by the synthesis tool. Make a point, from time to time to review the Final Report section which summarizes the chip resources used and performance. This design should not use any latches or flip-flops. To close the report file, either click the red X button in the upper right of the report display window, or click to select the report window title bar and then select
File => Close.
A test bench is analagous to a laboratory test bench, which has signal generators, and test gear. A test bench is special VHDL file that describes what the input will be will be, as can also be used to check that the corresponding outputs are correct. We will discuss later how to write your own test benches by hand, for now we will use the graphical program called Bencher to produce test bench files.
In regards to simulation, Webpack/ISE is a departure from the much older Foundation-Series tools which can only simulate fully synthesizable VHDL code and cannot support test benches. Test benches are an important aspect of VHDL, and their support in ISE is a welcome addition. ISE allows simulation to be based on either a hand written test bench, or a computer generated test bench produced by a graphial program like Bencher.
A more recent change to Webpack/ISE is the addition of a built-in simulator. Previous versions required the use of an external simulator such as Modelsim. In the upper left pane, double click the top-most fadd icon and examine the pop-up Project Properties window. The simulator field names the simulator that will be used. Have 'ISE Simulator' selected then click OK.
Lets get started by using Bencher to produce a test bench. In the Project Navigator Window, make the following selection by either clicking the New Source icon or pointing the mouse and left clicking:
Project => New Source
In the New dialog box, click to highlight the Test Bench Waveform entry, enter fadd_tb into the File Name field, verify that the Add to Project box is checked, and then click Next. Be carful to not use the name fadd here, as that is the name of your VHDL source file. The Select dialog box associates the new file with a VHDL entity to be tested. The entry fadd should already be highlighted. Click the Next button.
The next dialog box summarizes the data entered. Click Finish to start the HDL Bencher tool and open the Initialize Timing dialog box. The button indicating a combinatorial design should be checked, along with the following values listed. Click OK.
What the above data means, is that following a change in the input, the ouput will be checked 50ns later, and new inputs are possible 50ns after that. With this timing, the simulation time-step is 100ns. For this example you will manually set the input values for each time interval. To set the input to 001b at time 100ns, point to the center of time interval and click left. Continue, setting the values in the following intervals to 010b, 011b, 100b, 101b, 110b, and 111b, respectively.
Right click on the signal name 'sum' and select 'Add Divider' and in the pop-up window enter your name and click okay. You can select and use the mouse to move the selectede dividers and signal names anbout.
Select File=>Save and then close the Bencher window. In order to have Bencher produce a test bench that checks output, it is necessary to somehow tell Bencher what the expected output values are. For this purpose, we will simply examine the simulator results by hand.
ISE/Webpack provide several opportunities to use simulation to check the correctness of the VHDL code. Getting from VHDL code to a bit file that you can download into an FPGA is a two step process. The synthesis program essentially produces a list of basic parts that is your circuit. The implementation tool fits that list into the FPGA. As such, consider the following two simulation types:
Behavioral - A simulation performed using the VHDL code as-is. With this type, the simulator cannot provide much detailed timing information, so the simulation timing looks ideal.
Post Route - This is the whole enchilada in that it conatins all the timing information produced by the implementation tools and will be the most realistic. Since it involves the output of the synthesis program, these results may disagree with the behavioral simulation, and your understanding of what you want the VHDL file to contain.
In some situations, as when latches are accidentally inferred, the post route simulation may differ from the behavioral simulation. For this reason, do not rely solely on the behavioral simulation. Be sure to compare both sets of simulator results to the truth-table given earlier in this document.
A closing comment, double left clicking a signal value opens a window that can allows you to describe a pattern or use the pattern wizard to enter input in a way that is sometimes more convenient.
In the upper-left pane of the project manager, change the Sources for: choice to 'Behavioral Simulation'. Click left to select the fadd_tb file icon. In the lower left pane, click the '+' icon in front of the Xilinx ISE Simulator toolbox icon. Right click on 'Simulate Behavioral Model' and select Run. You may have to stretch to resize the simulation output window. As with Bencher, right click on the Sum icon and add a divider and insert your name.
To print out the waveform display select the following. If a default printer is not be selected, click the down-arrow next to the printer name field and select a printer.
File => PrintThere are options for producing a file that you can insert directly into a wordprocessor application like MS Word. One choice is to do a window dump. Click to highlight the simulation window, and press Alt-PrintScrn. Next open a graphics editor program like Paint and select Edit => Insert and then use Paint as you normally would to crop and then produce a file.
Hopefully there are no surprises left so that the implementation will be a simple thing. In rough terms, the job of implementation involves assigning resources like pins to your design. A so-called user constraint file (.ucf) is used for this purpose. First, create a blank .ucf constraints file.
Project => New Source
In the pop-up window click to select Implementation Constraints File and in the Filename field enter fadd, then click Next. The highlighted name fadd in the next window refers to the corresponding VHDL source file. Be careful which module you choose, it is possible to create a .ucf file for any design module in your project. Click Next and then Finish. An empty .ucf file has been created.
Once created, there are three option for editing the .ucf file.
In the upper left pane, set the 'sources for:' field to Synthesis/Implementation and click the '+' icon to the left of the fadd-DataFlow icon to reveal the fadd.ucf icon. Click left to select the fadd.ucf icon and in the lower left pane click the '+' icon to the left of the 'User Constraints' icon to reveal choices. Click right on 'Assign Package Pins' and select Run. In opening PACE, the tools perform an analysis step that takes a moment. Once PACE opens, change the values in the LOC column to match the following:
File => Save
File => Exit
A simple text editor is convenient for making simple changes, such as adding useful documentation comments to a .ucf file. A text editor is provided as an alternative to using the Constraints Editor. In the source panel of the project manages click once to select the .ucf file and in the process pane, double click on the 'Edit Constraints (Text)' option. In writing any project related text file it is worth your time to add a brief comment including the file name, a description of what the file is for, your name, and the date. Here is the completed .ucf file.
# fadd.ucf - pin assignments to demonstrate full adder # Jonathan Hill - Univ.Hartford CETA Sept. 6, 2007 NET "ain" LOC = "K13" ; # SW7 NET "bin" LOC = "K14" ; # SW6 NET "cin" LOC = "J13" ; # SW5 NET "cout" LOC = "P14" ; # LED1 NET "sum" LOC = "K12" ; # LED0 # End of Constraints file
Following any changes, be sure to save and close the file. The changes are not immediately reimplemented, you may have to rerun the tools. If a pop-up window appears, choose to use the '< >' symbols as icons and click 'OK'.
File => Save
File => Close
Original Author: Jonathan Hill (
jmhill at
hartford dot
edu )
Original Copyright Date:
Thu Sep 13 00:30:34 EDT 2007
Last Modified By: Jonathan Hill (
jmhill at
hartford dot
edu )
Last Modified Date:
Thu Sep 13 00:30:34 EDT 2007