Part 3 - VHDL with XC9536 and ISE 13.1

The Xilinx ISE tools allow you to use schematics, hardware description languages (HDLs), and specially designed modules to design logic based systems. In this tutorial you will enter VHDL code that models the full-adder shown below. Other parts discuss how to perform a functional simulation as well as simulation. Some readers will rightly object that this example fails to make use of blah, blah, blah... For such detail please refer to Xilinx, Digilent, and other literature. The primary goal of this document is to get you started on an adventure, using some conveniently available tools. Please make any changes that you deem necessary.

Complete full-adder schematic

For detail on installing the software and using the software on campus, please refer to:

Before starting the Xilinx ISE tools for the first time, manually set aside a directory for your projects. First open the selected drive. If you are working at home, open the C: drive. If you are working in computer lab, refer to the notes, Using Xilinx ISE 13.1 on campus. In the open drive folder, right-click and select:

New => Folder

and assign a name such as 'IseWork'.

Starting with a New Project

To start ISE, on the desktop click left to select the following:

Start => Programs => Xilinx ISE => ISE => Project Navigator

Select the version that is appropriate for your version of Windows. If a 'Tip of the Day' window pops up, click 'OK' to close it. In the ISE Project Navigator window, click left to make a new project:

File => New Project...

The first pop-up window involves the project location and project type. Enter the following then click Next.

To the right of the Location field click the three dot browse button ( ... ) and navigate to the work directory created above and click 'OK'.
The Location and Working directory should refer to the work directory
In the Name field type in 'fulladd'
The Location and Working directory fields will change to include the project name
Set the Top-level source type to 'HDL'

The next window involves selecting a part and several other options.

Evaluation Dev. Board: None Specified
Product Category: General Purpose
Family: XC9500 CPLDs
Device: XC9536
Package: VQ44
Speed: -5

Check the following then click Next.

Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISim (VHDL/Verilog)
Prefered Language: VHDL
Property Spec. in Project File: Store all values
Manual Compile Order: Not checked
VHDL Source Analysis Standard: VHDL-93
Enable Message Filtering: Not checked

The next window is a summary of the choices and values. Review the list then click 'Finish'.

Making a New VHDL Module

Next, make a new schematic. In the project navigator window, use the mouse to select:

Project => New Source...

In the pop-up window

Click the 'VHDL Module' icon
enter 'fadd' in the File name field.
Make sure the 'Add to project' item is checked

Click 'Next' and in the next window:

change the Architecture name to 'MyArch'
In the Port Name field of the first row enter 'ain, bin, cin'
In the Port Name field of the second row enter 'cout, sum' and change the direction to 'out'
Click 'Next'

In the next window review the data, then 'Finish'. After a few moments a new text editor appears. The editor may be more convenient to use undocked from the project window. Either right click on the 'fadd.vhd' tab below the schematic pane and select Float or in the project window select

Window => Float

Modify the file to look similar to the following, changing the author name and date.

-----------------------------------------------------------
-- fadd.vhd - fadd - Jonathan Hill - 17:13:09 09/12/2011
-- Full adder
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fadd is
    Port ( ain,bin, cin : in  STD_LOGIC;
           cout, sum : out  STD_LOGIC);
end fadd;

architecture MyArch of fadd is
  signal s1 : std_logic;
begin
  cout <= (ain and bin) or (ain and cin) or (bin and cin);
  s1 <= ain xor cin;
  sum <= s1 xor bin;
end MyArch;

Be sure that each of your VHDL design units contains at least the following:

File name, entity name
Your name and the date
A description of the relevance or what the design is

Final Steps

Now the final steps.

Dock the editor into the project Window => Dock
Save your work File => Save All
Under the Options pane or process pane look for the Design tab and click on it. You might have to click the left arrow (at lower right) to bring the Design tab into view.
Process Pane
Look in the Hierarchy pane to make sure that the Implementation button is pressed and fadd (fadd.sch) is selected.
In the process pane, click the '+' before 'Implement Design'
Double click on 'Synthesize - XST' and in a few moments a green check symbol should appear indicating success. Otherwise, examine the report in the console and make corrections to your code.

Your module is now complete. Be sure to make a printout. Finally a word of caution, the Xilinx tools use many self generated work files and on rare occasion the tools will become confused. If you want to save disk space or if the Xilinx tools start acting particularly odd, then at the top of the Project Manager window select:

Project => Cleanup Project Files

In the pop-up menu click OK.

Copyright Notice

This tutorial is written for students in the College of Engineering, Technology, and Architecture (CETA) at the University of Hartford, Connecticut, USA. Copyright is reserved by the author, but copies of this entire document may be made for educational use as-is, provided that this statement remains attached. The original version of this tutorial was written in great haste and constructive criticism is welcome.

Original Author: Jonathan Hill ( jmhill at hartford dot edu )
Original Copyright Date: Tue Aug 30, 2011
Last Modified By: Jonathan Hill ( jmhill at hartford dot edu )
Last Modified Date: Tue Aug 30 13:56:08 EDT 2011