Part 3 - Schematic Capture with XC9536 and ISE 13.1

The Xilinx ISE tools allow you to use schematics, hardware description languages (HDLs), and specially designed modules to design logic based systems. This tutorial discusses hierarchical schematic designs. In this tutorial you will enter the schematic of the full-adder shown below. Other parts discuss how to perform a functional simulation as well as simulation. Some readers will rightly object that this example fails to make use of blah, blah, blah... For such detail please refer to Xilinx, Digilent, and other literature. The primary goal of this document is to get you started on an adventure, using some conveniently available tools. Please make any changes that you deem necessary.

Complete full-adder schematic

For detail on installing the software and using the software on campus, please refer to:

Before starting the Xilinx ISE tools for the first time, manually set aside a directory for your projects. First open the selected drive. If you are working at home, open the C: drive. If you are working in computer lab, refer to the notes, Using Xilinx ISE 13.1 on campus. In the open drive folder, right-click and select:

New => Folder

and assign a name such as 'IseWork'.

Starting with a New Project

To start ISE, on the desktop click left to select the following:

Start => Programs => Xilinx ISE => ISE => Project Navigator

Select the version that is appropriate for your version of Windows. If a 'Tip of the Day' window pops up, click 'OK' to close it. In the ISE Project Navigator window, click left to make a new project:

File => New Project...

The first pop-up window involves the project location and project type. Enter the following then click Next.

To the right of the Location field click the three dot browse button ( ... ) and navigate to the work directory created above and click 'OK'.
The Location and Working directory should refer to the work directory
In the Name field type in 'fulladd'
The Location and Working directory fields will change to include the project name
Set the Top-level source type to 'Schematic'

The next window involves selecting a part and several other options.

Evaluation Dev. Board: None Specified
Product Category: General Purpose
Family: XC9500 CPLDs
Device: XC9536
Package: VQ44
Speed: -5

Check the following then click Next.

Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISim (VHDL/Verilog)
Prefered Language: VHDL
Property Spec. in Project File: Store all values
Manual Compile Order: Not checked
VHDL Source Analysis Standard: VHDL-93
Enable Message Filtering: Not checked

The next window is a summary of the choices and values. Review the list then click 'Finish'.

Making a New Schematic

Next, make a new schematic. In the project navigator window, use the mouse to select:

Project => New Source...

In the pop-up window

Click the 'Schematic' icon
enter 'fadd' in the File name field.
Make sure the 'Add to project' item is checked

Click 'Next' and then 'Finish'. After a few moments a new schatic window might be covered by the Design Summary window. Above the console pane, to the right click the 'fadd.sch' tab. The schematic capture tool is more convenient to use undocked from the project window. Either right click on the 'fadd.sch' tab below the schematic pane and select Float or in the project window select

Window => Float

You are now ready to insert components into the schematic

Inserting Components

If the Symbols pane and the Options panels are not already visible then select View => Panels and check to make those panes visisble. Next, do the following:

In the Categories list select: Logic
In the Symbols list select: and2

Now when you move the mouse to point in the schematic editor, an instance of a two input AND gate appears. Click left to place the AND gate into your schematic, and then click to insert two more AND gates. Continue, inserting an or3 gate and two xor2 gates, so the schematic looks similar to the following:

Gates for full-adder

To get a better view of the components, you can zoom in or out the view. The zoom-to-box choice has you use the mouse to draw a box to define the level of zoom. The zoom-to-full-view zooms out to display the entire schematic. The zoom-to-seleted zooms to display the selected components.

View => Zoom => In
View => Zoom => Out
View => Zoom => To Box
View => Zoom => To Full View
View => Zoom => To Selected

Inserting Wires

The next step is adding wires, and then adding I/O markers. To wire one device terminal to another first change to the wire mode. Once in the wire mode, the icon changes to cross-hairs. Entering the mode can be done several ways:

Add Wire Icon

Click the Add Wire icon
Below the ISE Schematic Editor toolbar, select Add => Wire
Enter the Control-W key pair
in the schematic area, right click and in the pop-up window select Add => Wire

Move the cross-hairs to the upper left XOR gate output pin till tiny boxes appear, and left click the mouse. Move the cross-hairs to the upper input gate of the right XOR gate. Left click the mouse so a wire is placed.

First wire placed

Add additional wires so the circuit looks like the figure below. To place a bend in a wire, left click. To move a wire, first press the escape key to change to the normal mode. Next point and left click to select a wire and then use the mouse to drag the wire. To attach a wire to another to form a connection point, point at the wire and left click.

Adder wires placed

To move a wire, point the mouse at it, press the left button, and drag the mouse to move the wire, then release the left button.

Input/Output Markers

A dangling wire has a connection on one end only. There are two methods to place a dangling wire. Start by changing to the wire mode, using a technique described above.

Point away from components and left click. Move the cross-hairs and connect to a component pin.
Point at a component pin, left click to start a wire. Move the cross-hairs, left click to place a bend in the wire, and then right click or press the escape key.

Add dangling wires so the circuit looks like the following:

Dangling wires added

Next, add I/O markers. To switch to the I/O marker mode do one of the following:

I/O Marker Icon

Click the I/O marker icon
Either below the ECS title bar or in the schematic area right click and select the following:
```
Add => I/O Marker
```

The cursor changes to cross-hairs with an attached marker icon. In the process pance, click the I/O marker direction radio buttons to Add an input marker. Point the cross-hairs at the upper left dangling wire end and left click to place an I/O marker. In a similar fashion, attach markers to other two dangling wires to the left.

Double click the upper left marker. In the pop-up window change the I/O marker font size to 32, look in the Category pane\ and click on 'Nets' then enter the name 'cin' into the Name field and then click 'OK'. Likewise, assign the names 'ain' and 'bin' to the middle and lower marker.

Input markers inserted in

Enter marker mode again, this time in the process pane, click to select 'Add an output marker'. Attach markers to the dangling wires to the right, and this time assign the names 'cout' and 'sum' to upper right and lower right dangling wires, respectively.

Internal Signal Names

It is a good idea to assign names to the wires inside your schematic, doing so will help you later to perform simulation.

Click the 'Add Net Name' icon
Add Net Name
In the Options pane, enter 'c1' in the name field. Move the mouse into the schematic and click the wire from the top most AND gate output.
Likewise, assign 'c2', 'c3', and 's1' so the schematic looks like the following:

Full adder circuit with names for internal signals

Title Block and Final Steps Including Checking the Design

To add a title block to the schematic:

click the 'Add Icon' button to enter the corresponding mode
select the General category pick the title component.
Place the title block near the lower right corner of the schematic.

You can zoom-in to get a better view of the title block. Next, double click the title block icon and in the pop-up window, enter the following into each field, then click 'OK'.

Title Field Text: Full Adder Circuit
Name Field Text: 'Your Name'

Your title block will look similar to the following:

Title block

Now the final steps.

Dock the schematic editor into the project Window => Dock
Save your work File => Save All
Under the Options pane or process pane look for the Design tab and click on it. You might have to click the left arrow (at lower right) to bring the Design tab into view.
Process Pane
Look in the Hierarchy pane to make sure that the Implementation button is pressed and fadd (fadd.sch) is selected.
Design Pane
In the process pane, click the '+' before 'Design Utilities'
Double click on 'Check Design Rules' and in a few moments a green check symbol should appear indicating success. Otherwise, examine the report in the console and make corrections to your schematic.

Your schematic is now complete. Be sure to make a printout. Finally a word of caution, the Xilinx tools use many self generated work files and on rare occasion the tools will become confused. If you want to save disk space or if the Xilinx tools start acting particularly odd, then at the top of the Project Manager window select:

Project => Cleanup Project Files

In the pop-up menu click OK.

Copyright Notice

This tutorial is written for students in the College of Engineering, Technology, and Architecture (CETA) at the University of Hartford, Connecticut, USA. Copyright is reserved by the author, but copies of this entire document may be made for educational use as-is, provided that this statement remains attached. The original version of this tutorial was written in great haste and constructive criticism is welcome.

Original Author: Jonathan Hill ( jmhill at hartford dot edu )
Original Copyright Date: Tue Aug 30, 2011
Last Modified By: Jonathan Hill ( jmhill at hartford dot edu )
Last Modified Date: Tue Aug 30 13:56:08 EDT 2011