Simple ALU Circuit - ECE534 - Fall '04-'05

An arithmetic logic unit (ALU) is a combinational logic component commonly found in a central processor unit (CPU). This lab provides an opportunity to experiment with a particularly simple ALU structure. Your design will be implemented using a Digilent Digilab II FPGA board and a matching Digilab IO1 board.

Behavior and User Interface

Your ALU model, illustrated below receives a function code, four-bit input values Ain and Bin, and produces the four-bit result Rx and three status flags Z, C, V. Based on the function code, the ALU performs one operation, that of addition, subtraction, left shift (LS), or unsigned right shift (RS). The shift operations always insert a low bit ('0') appropriately. The addition and subtraction operations operate on inputs Ain and Bin. The shift operations use Ain as the input.

ALU conceptual diagram

The following is an explanation of the status flags. Note that the meaning of the signals C and V is not defined in the context of the bitwise-AND operation or shift operation. Make a decision of the significance of these cases, you will be expected to explain in your report how you handled these details.

Z - Is high when the result equals zero
C - Is high when addition produces a carry out at the most significant bit position
V - Is high to indicate that addition may have caused two's complement overflow.

The overall user interface provides for the signals in the table below. It is recommended that you use switches to produce Ain and Bin. Pushbuttons can be used to produce the function code. LEDs can be used to display the results Rx and status flag bits. The switches, pushbuttons, and LEDs all act as positive logic devices so that logical inversion is not required.

signal	direction	description
Ain	input	A four bit value
Bin	input	Another four bit value
fnct	input	ALU function code
Z	output	Zero result flag
C	output	Carry-out signal from adder
V	output	2's complement overflow flag
Rx	output	four bit result

For the sanity of the instructor, PLEASE define your bit vectors with the most significant, highest number bit being left-most and least significant, lowest numbered bit (zero) right most. Thus inputs Ain and Bin will be defined to be of type std_logic_vector(3 downto 0). The operations will be performed according for the following values in fnct.

"00" = Addition
"01" = Subtraction
"10" = Right shift
"11" = Left shift

In your report you will also describe how the four function codes are expressed in the signal fnct. The pushbuttons are most convenient for producing the values for fnct. Be prepared to explain how you use the buttons. The following outlines the steps a user might follow to operate your ALU circuit:

Assign values to Ain and Bin.
Assign the selected function to fnct .
The state of Z, C, and V will correspond to the value produced by the ALU.
The bus signal Rx represents the results.

Implementation Details

This lab provides an excellent opportunity to practice your skills at hierarchical design. The ALU will be designed using only structural and simple data flow style descriptions. There is no need to go "overboard," one level of hierarchy is enough. Warning: I do not want to see the key-word process in use anywhere in your code. In designing your ALU, you will make use of full-adder components constructed using the data-flow technique.

The following table lists the cases that will serve to verify that your circuit works correctly. In this table it is understood that in vector signals, the most significant bit is left-most as least significant bit is the right-most. Be sure to replace the '?' symbols in the table with the correct 1 or 0 symbol, based on how your circuit handles those specific cases.

Verification Cases

Ain	Bin	Operation	Rx	Z V C
0011	0101	Add	1000	0 1 0
0011	1111	Add	0010	0 0 1
0011	0011	Sub	0000	1 0 1
0001	1111	Sub	0010	0 0 0
0011	`----`	LS	0110	0 `?` `?`
1100	`----`	LS	1000	0 `?` `?`
0011	`----`	RS	0001	0 `?` `?`
1011	`----`	RS	0101	0 `?` `?`

The Write Up

In performing the write-up for this lab be sure to reread the entire handout so that you don't overlook any points that you are expected to discuss. Use diagrams and figures along with suitable discussion to make each of your points clear.

How do the function codes represented by fnct correspond to ALU operations?
How are the switches, buttons, and signals Ain, Bin, and fnct coordinated?
In all cases, how are the status flag signals assigned values? In particular, fully explain the 2's complement overflow flag V.

Make sure to include the following items as content in your report

Introduction along with the conceptual diagram given above
Discussion of the implementation along with system block diagram. The diagram will show the structure of your circuit. Use a box to represent each significant component that you instantiate, or circuitry that you use.
Completed table listing the verification cases
Simulation results showing that your design works
In an appendix include an appropriately brief introduction that provides a list of all the modules as well as the source code for each component.
In an appendix include a suitable discussion and a table of the pin assignments made
The sign-off sheet

A warning; the conceptual diagram at the top of this document is not a complete system block diagram. To produce the diagram, show how multiplexer(s), full-adders, and other components are used to produce the overall design.

Sign Off Sheet

After demonstrating the final version of your project, make sure to have a member of the teaching staff sign and date the following:

Student Name:

Demonstrated final version of ALU project:

Copyright Notice

This lab handout is written for the ECE534 class - VHDL and Application. Copyright is reserved by the author, but copies of this document may be made for educational use as-is, provided that this statement remains attached.

Original Author: Jonathan Hill (jmhill@mail.hartford.edu)
Last Modified By: Jonathan Hill (jmhill@mail.hartford.edu)
Copyright Date: Thu Sep 9 14:31:10 EDT 2004
Last Modified Date: Thu Sep 9 14:31:10 EDT 2004