-- fad.vhd - Jonathan Hill oct. 8, 2005
-- Full adder data flow model
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fad is
    Port ( cin : in std_logic;
           ain : in std_logic;
           bin : in std_logic;
           cout : out std_logic;
           sum : out std_logic);
end fad;

architecture DataFlow of fad is
  signal sum1 : std_logic;
begin
  sum1 <= ain XOR bin;
  sum  <= sum1 XOR cin;
  cout <= (ain AND bin) OR (ain AND cin) OR (bin AND cin);
end DataFlow;