Xilinx ISE Schematic Capture

The Xilinx ISE tools allow you to use schematics, hardware description languages (HDLs), and specially designed modules in a number of ways. Schematics are drawn by using symbols for components and lines for wires. There are two ways you can produce your own symbols for a module. One way is to produce a diagram from a schematic. The second way is to produce a symbol from a description written using a hardware description language. In this tutorial you will do the following:

1. Enter the schematic of a single bit full adder

2. perform a behavioral simulation

3. Create a symbol from a schematic

4. Create a symbol from VHDL code (for the same full adder)

5. Use the full adder symbol to construct a four-bit ripple carry adder and again perform Behavioral Simulation.

Some readers will rightly object to the example in that it fails to make use of hardware features available in modern FPGAs.  The point however, is to get you started on an adventure, using the tools.  The first step of a long journey need not be that high-tech.

Before going any further, read the Preparing for ISE document, to prepare for using ISE either on your home computer, or on campus.

Starting ISE

To start Xilinx WebPACK ISE, either double click on the window icon matching that shown below, or make the following selection:

Start => All Programs => Xilinx ISE 7.1 i => Project Navigator

ISE 7.1i Project Navigator icon

Once the Project navigator window is open, make a new project.  Use the mouse to select:

File => New Project
 

In the New project window, enter data so the fields look like the following, then click OK.  If you are on campus review the Preparing for ISE document and make a suitable change. Of the choices, USB flash memory is the most convenient.

Project name and location

In the next window enter the following details and click Next.

Device and Design flow for the Project

Click Next on subsequent windows. Review the details finally and click Finish.

Entering the Schematic

Next, make a new schematic.  In the Project navigator window, use the mouse to select: I

Project => New Source

In the New source window, select Schematic and then click Next and then, click Finish to produce the new schematic and open the Schematic Editor window fadd.sch. 

New Source window

Before we caught up in details, the following is the single bit full-adder circuit that you will be entering:

Full adder schematic

The Xilinx Schematic capture tool opens and a new entry named fadd with a .sch extension appears in the Module View tab, in the Sources in Project pane which is in the upper left part of the Project navigator window.  Click the >> icon to expand the schematic window outside the Project Navigator. Once the schematic is done you can click the << icon to return it to the Project Navigator.

Inserting the Components

The next step is to insert components into the schematic and then use wires to interconnect the components.  The Schematic Editor is said to have modes, if you haven’t selected any component (as is the case initially) you are in normal mode where the mouse is represented by a mouse arrow. Click on the Symbols tab in left side of the Schematic window. In the categories window use the mouse to select the entry logic.

Categories windows

Next, in the Symbol window, which is below the Categories window, use the mouse to select the two input XOR gate named xor2.

Symbols windows

In making such a selection the Schematic Editor changes to the place components mode. In this mode, the mouse arrow is replaced with cross hairs and has a component attached.  To exit this mode and to enter again into the normal mode, either press the escape key or click the pointer icon.

Pointer icon

To place a component in the schematic, select a component from the component symbols list as described above.  Next, move the mouse pointer to the schematic, click left, and move the mouse to reveal the placed component. Place two xor2 components, and below them three and2 components.  Finally, slightly to the lower right place an or3 component. 

Newly placed components

To zoom in on a selected part of a schematic, either press F9 or select the following:

View => Zoom => To Box

Place the mouse cross-hairs just above and to the left of the components you placed.  Press and hold the left mouse button and drag the mouse so a box appears around the components, and then release the left mouse button. In zoom mode, the mouse arrow is replaced with cross-hairs.  To exit this mode, either press the escape key or click the pointer icon. Notice how the pull-down menu lists the corresponding function key for each zoom function.  To return to the full schematic view, either press F6 or select:

View => Zoom => Full View
 

Adding Wires

The next step is adding wires, and then adding I/O markers.  To wire one device terminal to another first change to the wire mode.  This can be done several ways.

Add Wire Icon

• Click the Add Wire icon
• Below the SCHEMATIC toolbar, select Add => Wire
• Enter the Control-W key pair
• In the schematic area, right click and in the pop-up window select

Add => Wire

Once in the wire mode, the icon changes to cross-hairs.  Move the cross-hairs to the output pin of the left XOR gate till four tiny black square boxes appear (this is the place where your wire connection should start), left click the mouse and drag.  Move the cross-hairs to the upper input pin of the right XOR gate till you again see the four tiny squares (end of wire). Here release the mouse so a wire is placed. 

First wire placed

If in connecting wires you have to stop somewhere in the middle (to bend) left click. At the place where you stop there will be a tiny red box. Then to complete the remaining connections again place you cross hairs at the red box (the correct position will be indicated by appearance of four tiny square boxes) and end at the required place as discussed above. Add additional wires so the circuit looks similar to the following.  To attach a wire to another to form a connection point, point at the wire and left click.  A small circle indicates all the connection points.

Connection in-between gates

A dangling wire has a connection at one end only.  There are two methods to place a dangling wire.  Start by changing to the wire mode.

• Point away from components and left click.  Move the cross-hairs and connect to a component.
• Point at a component pin, left click to start a wire.  Move the cross-hairs, left click to place a bend in the wire, and then press the escape key.

Add dangling wires so the circuit looks like the following:

Addition of dangling wires

Adding I/O Markers

Next, add I/O markers.  To switch to the I/O marker mode, do one of the following:

I/O Marker Icon

• Click the I/O marker icon
• Either below the Schematic title bar or in the schematic area right click and select the following:

Add => I/O Marker

The cursor changes to cross-hairs with an attached marker icon.  Do the following in Options tab. In the Add I/O Marker Options pane check the Add an automatic marker box and choose the orientation to be automatic. Point the cross-hairs at the upper left dangling wire end and left click to place an I/O marker.  In a similar fashion, attach I/O markers to the remaining four dangling wires.

Addition of I/o Markers

Press the escape key to return to normal mode.  Double-click the I/O marker of the upper left most wire to open the Object Properties window.  In the Name field change the entry to Xin. The PortPolarity field should show Input. Click OK.

In similar fashion, change the names of the middle and lower I/O markers to Yin and Cin, respectively. Also change the names of upper and lower I/O markers on the right to Sum and Cout(In both these cases the PortPolarity field should show Output). The schematic should look like this.

Naming the I/O markers

Adding Branches

The schematic becomes easier to understand and debug if the wire branches are named. To do this between the branch of wire between the two XOR gates, do the following. Click on branch name icon and do the following in Options tab. Check Name the branch box, in the Name field enter the name XinXORYin and check keep the name box. The cross hairs carry the name of the branch(XinxORYin). Point to the branch and left click to get the name on top of the branch. Similarly name all the in-between branches. The final schematic should be like this.

After the branches are named

Adding a Title Block

To add a title block to the schematic, click on Symbols tab. In the Categories window select the General and in Symbols window choose title.  Place the title block near the lower right corner of the schematic.  Zoom in to get a better view of the title block.  Use one of the following methods to change to the Add Text mode.

Add Text Icon

• Click the Add Text Icon
• Below the Schematic title bar select Add => Text
• In the schematic area right click and select Add => Text
• Enter the Control-T key combination

In the Options tab enter your name in Text value field and choose the text size to be forty (40). Move the cross-hairs to the Name field in the title block and left click.  Similarly, enter the title. The current date should already exist in the Date field.   The title block will look similar to the following:

Example Title Block

Checking the Schematic

The schematic is now completed.  To check the schematic, select the following:

Tools => Check Schematic.

The Schematic Check errors window will open. If an error is reported, click Error Msg or Error No field so a yellow report marker appears in the schematic indicating the location of the error. If you have a error go ahead and fix it and save the diagram and check the schematic again.  A correct schematic will not have any errors reported.  Below the Schematic title bar, click:

File => Save

There are two options, as to what comes next. To implement the design in an FPGA, the synthesis and implementation tools must be executed.

Behavioral Simulation of the schematic

The behavior of the system (whether a schematic or a HDL description) is verified by running it through a simulator. We will perform a Behavioral simulation here.  To perform a simulation a special file called a test bench is required. The test bench can either be a hand-coded or one generated by the Xilinx HDL Bencher tool.  The HDL Bencher tool provides a simple graphical means to give the inputs, which is converted to a test bench file, which the simulation tools will use. To create the HDL bencher do the following.  In the Project Navigator window, select the following:

Project =>New Source

In the New dialog box, highlight the Test Bench Waveform entry, enter fadd_tb into the File Name field, and verify that the Add to Project box is checked, and then click Next.  In the Select dialog box used to choose the top-most design module, the entry fadd should already be highlighted.  Click the Next button.

This next dialog box summarizes all data entered thus far and gives you a last chance to back-up to make changes.  Click Finish to start the HDL Bencher tool.  In the Initialize Timing dialog box, check the button indicating a Combinatorial design , along with the values listed. 

• Check outputs: 50ns
• Assign inputs: 50ns
• Initial length of test bench : 1000ns

Click OK. With this timing the basic unit of simulated time will be 100ns.  In this example you will manually set the input values for each time interval.  To set the input to 001b between times 100ns and 200ns with Cin, Xin being 0 and Yin being 1, in Yin field point anywhere in the time interval(100 – 200ns) and left click.

Setting input Yin high on 100ns

Continue, setting the values in the following intervals to 010b, 011b, 100b, 101b, 110b, and 111b, respectively.  In the HDL Bencher window, use the mouse to select:

File => Save

Next, close the Bencher window

File => close

In the Module View tab in Sources in Project pane of the Project Navigator window, you can notice the test bench fadd_tb.tbw below fadd.sch. Click left to highlight the file fadd_tb.tbw.  In the Process View tab in Processes for Source pane, right-click on Simulate Behavioral Model and in the pop-up window select Run.  If you cannot see the entry, left click the + icon to left of the toolbox icon for ModelSim Simulator.  In a few moments the simulator opens a lot of windows. Below is a snapshot of the ModelSim 3 Starter 6.0a showing the windows we will be interested in this tutorial.

ModelSim snapshot

In the right pane of the ModelSim window where the fadd_tb.vhw file is left click on the wave. This window gives us the Behavioral Simulation results. In the upper right part of the window left click on the icon to expand the window outside the ModelSim. Maximize the window and do the following.

View => Zoom => Zoom Full.

Click on the icon to zoom even further.

Be sure to examine and verify the results.

Behavior Simulation Results

 As soon as the inputs change, the outputs change. There will be no propagation delay in this simulation.  Clicking on can zoom out the waveform.

Creating a Symbol from the schematic

In the Schematic window select the following:

Tools => Symbol Wizard

In the Symbol wizard window that opens check on Using schematic in Pin Name Source Category. Select fadd in Using schematic field. Also check on Do not use Reference symbol in the Shape Category and within it Rectangle. Click Next. In the next window that appears verify if Xin, Yin and Cin have their polarities as Input and Cout and Sum have their polarities as Output. Click Next. In the next window that opens the let the default values of Pin and symbol size remain as it is. Click on Next. The next window gives you a final opportunity to make changes to the new symbol.  No changes are needed here, so click on Finish. A symbol for the full adder has been created from schematic of a full adder and fadd.sym file opens.

Introduction to VHDL

VHDL stands for VHSIC Hardware description Language. VHSIC stands for Very High Speed Integrated-circuit Consortium. This language provides a means of specifying a digital system over different levels of abstraction. A VHDL module can represent a system in

1. Lower level of abstraction where nothing is hidden and the circuit is discussed in detail

2. Higher level of abstraction where the implementation details of lower levels are hidden.

An analogy is that if you describe a OR gate in VHDL module and in an another VHDL module describe the ADDER Circuit which uses the previously defined OR gate, the ADDER module is a higher level module compared to the OR gate module. Every module in VHDL consists of an entity and architecture. An entity defines the component or module name, and it’s input /output ports and related declarations. Architecture specifies the relationships between the input ports and the output ports.

Creating a Symbol from a VHDL module.

Right click on the following link for the VHDL file for single bit adder and click on Save Link As and save the file in the directory you are working. VHDL code for single bit adder. In your Project Navigator window toolbar click on

Project => Add Source.

In the new window that opens, highlight fad.vhd file within the folder adder and click Open. In the Choose Source Type window that opens highlight VHDL Design File and click OK. In the Module view tab in the Sources in Project pane you can notice the entry of fad.vhd file. This is your VHDL Design file. Double click this to open the text editor, which has a skeleton of your new VHDL file. Enter your name in the My Name field. No other changes are required to the file. Since you are not modifying the code, there is no need to run the synthesis tools for this VHDL module. Save the code into a project directory.

File => Save.

For this tutorial we do not assume that you know much about VHDL. If you are curious, double click the file name in the left sources pane to open the file and examine it. In VHDL it is possible to use different styles to describe a circuit, this file use a style called data-flow. Note that the file is simply a text representation of the same circuit given above. If you are interested in knowing even more about VHDL click on following link. More on VHDL

Behavioral Simulation of a VHDL module

Next perform a Behavioral simulation in the same way as the one you did for schematic.  The only difference this time is you create a test bench file called fad_tb and choose the entry fad as the source file. Enter the inputs the same way you did for schematic simulation. Run Simulate Behavioral Model on fad_tb.tbw and you should see the same output as the schematic simulation.

Creating a symbol from a VHDL module

Click to highlight fad.vhd module in the Module View tab. In the Process View tab right click on Create schematic symbol and choose Run. If you don’t see the Create schematic symbol icon left click on the Design Utilities icon. Once the process is completed a symbol has been created. You can then open the symbol and make changes to it if you like.

A Four-Bit ripple carry Adder from Single bit adder schematic

Now we will discuss creating a four-bit ripple carry adder from the single bit adder schematic. The four-bit adder is a higher-level module compared to the single bit adder.

In the Project Navigator window open a new schematic and name it fourbitsch.  In the Categories window within the Symbols tab of schematic fourbitsch click to select <c:/ISE 7 . 1 /adder> and in the Symbols window in the same tab select fadd. 

Placing Instances

Move the cross-hairs and place four instances of the full-adder, one below the other. Check if all of them are titled fadd.  The bottom most fadd adds the Least Significant bit’s of the inputs and the upper most fadd adds the Most significant bits. Insert wires to connect each Cout pin to its next Cin pin starting from the bottom as shown below.  From the Category window click on General. In the symbols window click on gnd and insert the ground symbol and wire it to the lowest Cin pin.

.  Placing four instances of the fadd and inter connecting it.

Adding Buses, Bus Taps

A bus is made, first by placing a wire in the schematic and then naming the wire as a bus.  Look at the figure below to see how to place the wire.  To end the wire, left click to place a bend, then press the escape key.  Next, attach the I/O marker, and press the escape to return to normal mode.  Double click the I/O marker and in the pop-up window change the Name field entry to Xval(3:0) . The PortPolarity field should by default be Input as this is an Input bus. Click OK. 

A first bus

Now that an Input bus is got, attach four bus tap icons to the bus wire. Click on the bus tap icon or choose Add => Bus tap from the Schematic tool bar. In the Add Bus tap options which appears under the Options pane, click on Left (as for the Input bus Xval(3:0), we add Input bus tap icons from the bus to the input pins of fadd(In this case input Xin pins)). Place the cross-hairs so that bus taps are connected with bus wire as shown and attach wires between the bus taps and input Xin pins. Each of these new wires must next be named.  Name the upper most bus-tap wire as Xval (3) so that the name appears on top of the bus tap wire. In similar fashion, name the remaining bus-tap wires, in successive downward fashion as Xval (2), Xval (1) and Xval (0) respectively. Name the branch wires connecting Cout pins to the next Cin pins starting from the bottom as Cout1, Cout2 and Cout3 respectively.

Bustaps and bustap wires

In the same fashion as above, add another bus with an input I/O marker named Yval(3:0).  Add bus taps, bus tap wires and in successive fashion from top to bottom, name the bus-tap wires as Yval (3), Yval (2), Yval (1) and Yval (0) respectively. Add a bus with an output I/O marker named Sum (3:0).  Add bus taps (only change is that since this is an Output bus, in the Add Bus Tap Options click on Right button), and add bus tap wires. In successive fashion from top to bottom, name the bus-tap wires as Sum (3), Sum (2), Sum (1) and Sum (0) respectively. Attach a wire to the MSB carryout pin (Cout) and an output I/O marker pin.  Name the I/O block pin Cout. Recheck your schematic with the schematic shown below.

Final schematic

To finish the schematic, add a title block and insert your name and title fourbit.

Save the schematic and check it for errors.

Behavioral Simulation of the four-bit adder

Add a test bench waveform file named fourbitsch_tb for the four-bit adder schematic fourbitsch in the same way as before. In the HDL bencher, for multibit input signals (like Xin & Yin), by default, the value entered is an unsigned decimal number.  To enter numbers of other types (like binary or Hexadecimal) right click on the waveforms and choose the desired type. Once the values are entered save the waveform and Run Simulate Behavioral Model on fourbitsch_tb.

Add signals to waveform

Adding signals helps in analyzing the simulation results better. Before examining the waveform add signals Cout1,Cout2 and Cout3 to simulation results by the following steps.

1. In the Workspace window in ModelSim Starter window select uut instance.

2. In the Object window you will find that signals Cout1,Cout2 and Cout3 have been added apart from the existing Inputs and Outputs.

3. To add signal Cout1, right click on Cout1 and choose Add to Wave => Selected signals .

Similarly add signals Cout2 and Cout3. (uut stands for unit under test which in this case is the four bit schematic. If you click on the + icon next to uut you can see all the four single bit adders and the ground, and hence by clicking on these you can add the signals which belongs to these components to the wave default. For this Project you don’t need to do this. This is just to illustrate how you can look into your lower level module signals also).

Now that you have added the signals expand your wave default window outside the ModelSim starter. Maximize it, click on the Restart button and in Restart window that opens make sure that everything is checked and then click Restart. Now click on Continue run button . Analyze the waveform. It should be similar to the one below.

Simulation results for a four bit adder

Create a symbol for four bit adder

Now create a symbol for the four-bit adder. The only change is that this time in the Symbol wizard window, in the Using schematic in Pin Name Source Category, select fourbitsch. The rest is the same as the one you did for single bit adder schematic. Once a symbol for the four bit full adder has been created from it’s schematic the fourbitsch.sym file opens with the following symbol. Check the symbol.

Four bit adder symbol

Create a four bit adder schematic using single bit adder VHDL module and Simulate it

In a similar way create a schematic called fourbitvhd and use the fad symbol of single bit adder (got from the VHDL source code) to create a four bit adder similar to fourbitsch. The schematic whether you create from a VHDL code or a lower level schematic is the same and should behave the same way. After creating the schematic, create a HDL bencher, give the inputs and check the Simulate Behavioural Model. It should be same as the one for fourbitsch. Also create a symbol for it.

---

Copyright Notice

This tutorial is written for students in the College of Engineering, Technology, and Architecture (CETA), at the University of Hartford.  Copyright is reserved by the author, but copies of this document may be made for educational use as-is, provided that this statement remains attached.  The original version of this tutorial was written in great haste.  Later versions result from periodic improvement.  Constructive criticism is welcome and may be credited. 

Original Author: Jonathan Hill ( jmhill at hartford dot edu )
Original Copyright Date: Thu Oct 6 00:20:17 EDT 2005
Last Modified By: Shreekrishnan Venkatesh and Jonathan Hill ( jmhill at hartford dot edu ) Last Modified Date: Thu Oct 6 00:20:17 EDT 2005

---