Simple ALU Circuit - EE591 - Fall '01-'02
An arithmetic logic unit (ALU) is a component commonly found in a central
processor unit (CPU). This lab provides an opportunity to experiment
with a particularly simple ALU structure. Your design will be implemented
using a Digilent Digilab XLA5 development board.
Behavior and User Interface
Your ALU model, illustrated below receives a two bit function code, three-bit
input values Ain and Bin, as well as the three-bit output value Rx and
three status flags, Z, C, V. Based on the value in fnct, the ALU
performs addition, subtraction, bitwise AND, or a bitwise OR operation.
ALU conceptual diagram
The ALU also produces the following signals:
-
Z - Is high when the result equals zero
-
C - Is high when addition or subtraction produces a carry out at the most
significant bit position
-
V - Is high to indicate that addition or subtraction of 2's complement
numbers caused overflow
The overall user interface provides for the signals in the table below.
Note that since the switches act as negative logic devices, in the up position
each switch produces logic low. The suffix _n used in the signal
names below implies that the corresponding signals are the ones complement
of the corresponding internal signals.
|
signal
|
direction
|
description
|
|
Ain_n
|
input
|
A three bit value
|
|
Bin_n
|
input
|
Another three bit value
|
|
fnct_n
|
input
|
two bit ALU function code
|
|
Z
|
output
|
Zero result flag
|
|
C
|
output
|
Carry-out signal from adder
|
|
V
|
output
|
2's complement overflow flag
|
|
Rx
|
output
|
three bit binary output
|
The following outlines the steps a user might follow to operate your
ALU circuit:
-
Assign values to Ain_n and Bin_n.
-
Assign the selected function to fnct_n .
-
The state of Z, C, and V will correspond to the value
produced by the ALU.
-
The bus signal Rx represents the results.
Implementation Details
This lab provides an excellent opportunity to practice your skills at hierarchical
design. The ALU will be designed using only structural and
data
flow style descriptions. I do not want to see the key-word process
in use anywhere in your code. In designing your ALU, you will make
use of full-adder and multiplexer components constructed using the data-flow
technique. The following table lists the cases that will serve to verify
that your circuit works correctly. In this table it is understood that
for vector signals, the most significant bit is left-most as least significant
bit is the right-most.
Verification Cases
| Ain |
Bin |
Operation |
Rx |
Z V C |
| 001 |
001 |
Add |
010 |
0 0 0 |
| 001 |
001 |
Subtract |
000 |
1 0 1 |
| 001 |
011 |
Add |
100 |
0 1 0 |
| 110 |
011 |
Subtract |
011 |
0 1 1 |
| 001 |
010 |
AND |
000 |
1 0 0 |
| 111 |
111 |
AND |
111 |
0 0 0 |
| 000 |
000 |
OR |
000 |
1 0 0 |
| 011 |
101 |
OR |
111 |
0 0 0 |
The Write Up
In performing the write-up for this lab be sure to answer the following
questions. Use diagrams and figures along with suitable discussion
to make your points clear.
-
How do the function codes represented by fnct correspond to ALU
operations?
-
How are the switches and signals Ain, Bin, and fnct
coordinated?
Make sure to include the following items as content in your report
-
Introduction along with the conceptual diagram given above
-
Discussion of the implementation along with system block diagram
-
Source code for each component, along with suitable discussion
-
Simulation results showing that your design works
-
Only the pin assignments made in the .ucf file along with suitable discussion
-
The sign-off sheet
A warning; the conceptual diagram at the top of this document is not a
complete system block diagram. To produce the diagram, show how the multiplexer(s),
full-adder, and other components are used to produce the overall design.
Sign Off Sheet
After demonstrating the final version of your project, make sure to have
a member of the teaching staff sign and date the following:
Student Name:
Demonstrated final version of ALU with registers project:
Teaching staff member name and date:
Copyright Notice
This lab handout is written for the EE591 class - VHDL and Application.
Copyright is reserved by the author, but copies of this document may be
made for educational use as-is, provided that this statement remains
attached.
Original Author: Jonathan Hill (jmhill@mail.hartford.edu)
Last Modified By: Jonathan Hill (jmhill@mail.hartford.edu)
Last Modified Date: Sun Sep 23 17:18:06 EDT 2001